Top Design Engineer Jobs in Delhi

Design multilayer PCBs for energy IoT devices, finalize schematics and layouts with embedded teams, optimize for DFM and EMC, select components for mass production, run signal/thermal/power simulations, debug prototypes, and collaborate with vendors/EMS to bring boards to production.

Design rooftop and ground-mounted solar power plants, conduct preliminary site surveys, prepare bills of materials, PVSyst models, and plant layouts, and support presales through order closure. The role also contributes to process development and requires frequent city and PAN India site visits. Initial training is based in Ahmedabad for three months.

Designs and optimizes carrier network solutions for RFPs and RFQs, serving as a network planning subject matter expert. Evaluates technologies, develops transition architectures, analyzes network economics, and creates automation tools for sales engineering. Requires expertise in optical link budgets, nonlinear modeling, capacity planning, Layer 1 networking, carrier architectures, WDM, IP/MPLS, scripting, Excel, and SQL. The role collaborates with product, sales, optical, software, and global teams.

Design and build interfaces across HUD’s AI data platform and marketplace. Translate complex agent runs, evaluation results, reward signals, and reinforcement learning workflows into clear, actionable products. Partner with users, researchers, and engineers; conduct user research; ship and refine experiences; establish reusable interaction patterns; and maintain high standards for usability, visual quality, and implementation.

Designs and develops mechanical and electromechanical test fixtures, environmental test systems, and specialized tooling for optical networking products. Responsibilities include CAD modeling, engineering drawings, BOMs, tolerance studies, documentation, fabrication support, assembly, troubleshooting, validation, and deployment. The role collaborates with engineering teams, technicians, suppliers, manufacturing partners, and vendors to deliver reliable, manufacturable hardware solutions throughout the product development lifecycle.

Designs and implements DFT architectures and specifications for ASIC/SoC products. Responsibilities include scan insertion, ATPG pattern development, compression and clock-control insertion, optimizing test coverage and power, and pre- and post-silicon verification and debug. The role also requires gate-level simulation, failure analysis, scripting, and collaboration across product teams.

Design and verify complex CPU/SoC IP by planning verification, building constrained-random UVM or C/C++ test environments, or using formal SVA tools. Debug RTL (Verilog) in simulation/emulation, write functional coverage, and close verification holes to meet tape-out requirements.

Create and modify 3D mechanical part models using NX or other CAD software. Read mechanical drawings, assemble parts including large assemblies, and extract engineering drawings from 3D models. Teamcenter or other PLM experience is preferred. Candidates must hold a B.Tech, B.E., or Diploma in Mechanical Engineering and have at least two years of 3D CAD experience.

Lead verification for complex CPU/SoC IP and subsystems: define verification strategies and test plans, build verification environments, run and debug simulations/emulations, apply random-stimulus and coverage-driven techniques, and mentor engineers while improving verification methodologies and tools.

Lead mechanical design for consumer electromechanical products from concept through production. Responsibilities include CAD modeling, prototyping, testing, thermal/fluid/structural analysis, cross-functional collaboration, DFM/DFA, tolerance analysis, and manufacturing ramp support in Asia. The role requires designing plastic, metal, and soft goods components integrated with sensors and actuators, supporting high-volume manufacturing, and traveling to China as needed.

Design and build interfaces for HUD’s AI agent training, evaluation, and marketplace products. Translate complex reinforcement learning workflows, agent runs, evaluation results, reward signals, and quality feedback into clear, actionable experiences. Collaborate with users, researchers, and engineers to ship polished products, conduct user discovery, improve usability, and develop reusable interaction patterns.

Design and verify digital integrated circuits for TI products, including processor, memory-management, multicore, and cache architectures. Responsibilities include defining specifications, analyzing architecture trade-offs, participating in design reviews, supervising IC layouts, developing behavioral models, characterizing prototypes, creating test specifications, and coordinating with test and product engineering teams to support product releases.

Designs high-speed mixed-signal communication chips and digital circuits interfacing with analog circuitry. Responsibilities include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging, test method development, specifications, application materials, datasheets, and demo boards. Collaborates closely with analog and digital engineering teams to solve complex problems and deliver projects on time.

Designs high-speed mixed-signal communication chips and digital circuits interfacing with analog circuitry. Responsibilities include RTL coding, simulation, synthesis, timing closure, verification, evaluation, and debugging at circuit and behavioral levels. The role also develops test methods, specifications, application materials, data sheets, and demo boards while collaborating closely with analog and digital engineering teams.

Owns product development end to end by researching user problems, defining solutions, designing interfaces and prototypes in Figma, building production-ready React experiences, and iterating based on user behavior. The role combines product management, UX and visual design, and frontend engineering while improving workflows, component quality, responsiveness, accessibility of interactions, and design consistency.

Design and coordinate MEPF systems for building projects: produce detailed CAD/Revit drawings, perform load calculations and sizing, ensure code compliance, visit sites, integrate with architectural/structural teams, apply BIM workflows and sustainable/energy-efficient solutions, maintain project documentation, and mentor junior engineers.

Lead full-chip or large-block physical implementation from netlist to GDSII. Drive floorplanning, placement, CTS, routing, STA timing closure, DRC/LVS/EM/IR signoff, ECOs, hard-macro integration, PPA optimization, and automation scripting while collaborating with RTL, architecture, verification, and foundry teams.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Design and simulate transistor-level analog/mixed-signal IC blocks (amplifiers, converters, power circuits), define architectures, integrate blocks into mixed-signal systems, present results to teams/customers, support layout, lab evaluation and test, mentor others, and improve design methodologies to meet power, timing and functional objectives.

Own end-to-end UI/UX and frontend implementation: design user flows, craft high-fidelity prototypes, build responsive React+TypeScript interfaces, implement scalable component architecture, integrate with REST/GraphQL APIs, optimize performance, and collaborate with backend and product teams in a regulated life-sciences context.

Lead development, optimization, and verification of digital silicon IP from model to bring-up. Create and maintain specs, block diagrams, and documentation. Characterize IP performance using industry-standard tools and flows, including FPGA simulation and emulation. Collaborate with architecture, physical design, and software teams and lead verification engineers.

Design and implement RTL and microarchitectural components for SoC/IP using SystemVerilog/Verilog. Optimize PPA, collaborate with verification and physical design teams, support integration, timing closure, simulation, GLS, and silicon bring-up, and contribute to design documentation and reviews.

As a Demo Engineer, you support pre-sales by designing AI-driven demos and proof of concepts, collaborating closely with teams to showcase Cresta's capabilities.