Top Design Engineer Jobs in Delhi

Design façade hardware (sheet metal brackets, louvers, structural frames). Create accurate 2D/3D models in SolidWorks or AutoCAD. Ensure load-bearing, thermal, and safety compliance. Collaborate with fabrication and testing teams to support production and validation.

Design and coordinate MEPF systems for building projects: produce detailed CAD/Revit drawings, perform load calculations and sizing, ensure code compliance, visit sites, integrate with architectural/structural teams, apply BIM workflows and sustainable/energy-efficient solutions, maintain project documentation, and mentor junior engineers.

Design multilayer PCBs for energy IoT devices, finalize schematics and layouts with embedded teams, optimize for DFM and EMC, select components for mass production, run signal/thermal/power simulations, debug prototypes, and collaborate with vendors/EMS to bring boards to production.

Lead full-chip or large-block physical implementation from netlist to GDSII. Drive floorplanning, placement, CTS, routing, STA timing closure, DRC/LVS/EM/IR signoff, ECOs, hard-macro integration, PPA optimization, and automation scripting while collaborating with RTL, architecture, verification, and foundry teams.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Design and develop electronic hardware from concept to production, including schematic capture and multilayer PCB design, prototyping, bring-up, debugging, testing, and validation. Collaborate with firmware, mechanical, and manufacturing teams, support R&D and continuous improvements, and ensure compliance with design and quality standards.

Design and implement high-speed wireless communication systems on FPGA using VHDL/Verilog/SystemVerilog. Develop and verify RTL, implement modulation/demodulation (QPSK, QAM, OFDM), integrate with multi-core processors, troubleshoot performance issues, and lead technical project teams to meet cost and schedule targets.

Develop and verify shuttle layout for TI process nodes and tapeouts, ensure DRC and reticle compliance, collaborate with process and PDK teams, and create AI-driven automation tools to accelerate execution.

Design and simulate transistor-level analog/mixed-signal IC blocks (amplifiers, converters, power circuits), define architectures, integrate blocks into mixed-signal systems, present results to teams/customers, support layout, lab evaluation and test, mentor others, and improve design methodologies to meet power, timing and functional objectives.

Design and verify high-speed mixed-signal communication and high-performance digital circuits. Perform RTL coding, simulation, synthesis, timing closure, verification, and debugging at circuit and behavioral levels. Prepare test methods, specifications, datasheets, and demo boards. Collaborate with analog and digital teams and manage multiple tasks to deliver projects on time.

Own end-to-end UI/UX and frontend implementation: design user flows, craft high-fidelity prototypes, build responsive React+TypeScript interfaces, implement scalable component architecture, integrate with REST/GraphQL APIs, optimize performance, and collaborate with backend and product teams in a regulated life-sciences context.

Build production-quality, pixel-accurate UI components and interactions in React Native; prototype in Figma with designers; own the design system and component library; improve performance, animations, and cross-platform UI architecture; define design-to-dev tooling and collaborate across design and engineering.

Design, develop and integrate building management and controls for modular datacenter MEP systems. Own control architecture, PLC/HMI/SCADA programming, protocols, vendor review, FAT/SAT commissioning, troubleshooting, and mentor junior controls engineers while aligning with cybersecurity and IT requirements.

Lead verification for complex CPU/SoC IP and subsystems: define verification strategies and test plans, build verification environments, run and debug simulations/emulations, apply random-stimulus and coverage-driven techniques, and mentor engineers while improving verification methodologies and tools.

Lead verification of complex CPU/SoC IP: plan verification, build constrained-random UVM/SystemVerilog or C/C++ test environments, use SVA/formal tools, debug RTL (Verilog) in simulation/emulation, develop tests and coverage, and close verification gaps to meet tape-out requirements.

Design and verify complex CPU/SoC IP by planning verification, building constrained-random UVM or C/C++ test environments, or using formal SVA tools. Debug RTL (Verilog) in simulation/emulation, write functional coverage, and close verification holes to meet tape-out requirements.

As a Design Verification Engineer, you will verify designs for analog and mixed signal electronics, develop verification strategies, and collaborate with teams throughout the development process.

As a Design Verification Engineer, you will ensure the quality of advanced RADAR products, involving verification of IP, Subsystem, and SoC designs, collaborating with cross-functional teams, and developing robust verification methodologies.

Lead development, optimization, and verification of digital silicon IP from model to bring-up. Create and maintain specs, block diagrams, and documentation. Characterize IP performance using industry-standard tools and flows, including FPGA simulation and emulation. Collaborate with architecture, physical design, and software teams and lead verification engineers.

Design and implement RTL and microarchitectural components for SoC/IP using SystemVerilog/Verilog. Optimize PPA, collaborate with verification and physical design teams, support integration, timing closure, simulation, GLS, and silicon bring-up, and contribute to design documentation and reviews.

Lead verification strategy and execution for complex digital and mixed-signal designs. Architect UVM/SystemVerilog environments, develop advanced test benches, define coverage metrics, lead debug and post-silicon validation, mentor junior engineers, and drive methodology improvements while collaborating with design teams and customers.

As a Demo Engineer, you support pre-sales by designing AI-driven demos and proof of concepts, collaborating closely with teams to showcase Cresta's capabilities.

The Staff Engineer leads analog and mixed-signal block design, conducts design reviews, mentors junior engineers, and develops methodologies for advanced technology applications.