The Principal Design Engineer is responsible for design verification of interconnect IP, including crafting and executing verification plans, coverage collection, and collaborating with cross-functional teams. The role demands strong technical skills and experience in design verification along with knowledge of interconnects and related programming languages.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities
- Design Verification for interconnect IP
- Relevant experience in interconnect and subsystems is strongly preferred
- Crafting verification plans and executing on those plans to verify highly complex and configurable designs.
- Responsible for coverage collection and closure
- Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
Required Skills and Experience:
- 8+ years of design verification experience
- BS (or higher) in EE/Computer Engineering
- Strong technical and interpersonal skills
- Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
- Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
- Experience with development of fully automated flows
- Exposure to scripting languages like Perl, Unix shell or similar languages
- Experience with Formal Verification will be a plus
- Experience with Gate Level Simulations
- Excellent written and oral communication skills necessary
We’re doing work that matters. Help us solve what others can’t.
Top Skills
System Verilog
Uvm
Cadence Design Systems Noida, Uttar Pradesh, IND Office
Plot Nos 57 A, B, C, 11 & 10 Noida Special Economic Zone, PO NSEZ -, Noida, India, 201305
Similar Jobs
Be an Early Applicant
The Principal Design Engineer will develop performance models for DDR memory controller architectures, analyze trade-offs, automate performance metrics generation, and collaborate with Memory Architects. A strong foundation in hardware modeling and performance principles is required.
Be an Early Applicant
The Principal Design Engineer is responsible for the integration, customization, and post-silicon bring-up of CDNS DDR IP subsystems. This role involves resolving complex implementation issues, supporting integration reviews, performing simulations for functionality, and enhancing customer communication and experience.
Be an Early Applicant
The Technical Lead will develop scalable web applications using Angular, mentor junior staff, lead technical teams, and implement best practices. Responsibilities include application design, management of mono repos with NX, and developing robust architectures while ensuring code quality and team collaboration in Agile methodologies.
What you need to know about the Delhi Tech Scene
Delhi, India's capital city, is a place where tradition and progress co-exist. While Old Delhi is known for its rich history and bustling markets, New Delhi is defined by its modern architecture. It's clear the region places a strong emphasis on preserving its cultural heritage while embracing technological advancements, particularly in artificial intelligence, which plays a central role in shaping the city's tech landscape, fueled by investments in research and development.
