The Principal Design Engineer is responsible for the integration, customization, and post-silicon bring-up of CDNS DDR IP subsystems. This role involves resolving complex implementation issues, supporting integration reviews, performing simulations for functionality, and enhancing customer communication and experience.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Position Requirements
- M.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)
- Experience - 7+ years
- sound knowledge of DDR4/5, LPDDR4/5 IP.
- Hands on design/verification experience on DDR protocol
- Exposure to DDR Integration and Verification at SOC Level
- Exposure to Silicon Bring-up/Testing for DDR.
- Hands on design/verification experience on AMBA based protocols like AXI, AHB, APB
- Experience on cadence tools
- Exposure to Lint/CDC, Synthesis, Static Timing Analysis review
- Exposure to all major IC implementation, design, and verification tools.
- Willing to travel to customer sites worldwide.
- Working with global (US, west coast, and east coast) teams, which work in different time-zones.
- Primary Responsibilities:
- Responsible for supporting integration / customization / post silicon bring up of CDNS DDR IP subsystems.
- Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
- Support DDR Controller and PHY SOC integration reviews, and integration questions.
- Perform RTL and gate level simulations to verify functionality.
- Assist customers with gate level simulations and timing closure.
- Participate in development of CDNS documentations and checklists for customers.
- Support post silicon bring-up and deployment activities by our customers.
- Enhance customer experience by providing prompt updates to customers.
We’re doing work that matters. Help us solve what others can’t.
Top Skills
Computer Engineering
Electrical Engineering
Electronics Engineering
Cadence Design Systems Noida, Uttar Pradesh, IND Office
Plot Nos 57 A, B, C, 11 & 10 Noida Special Economic Zone, PO NSEZ -, Noida, India, 201305
Similar Jobs
Be an Early Applicant
The Principal Design Engineer is responsible for design verification of interconnect IP, including crafting and executing verification plans, coverage collection, and collaborating with cross-functional teams. The role demands strong technical skills and experience in design verification along with knowledge of interconnects and related programming languages.
Be an Early Applicant
The Principal Design Engineer will develop performance models for DDR memory controller architectures, analyze trade-offs, automate performance metrics generation, and collaborate with Memory Architects. A strong foundation in hardware modeling and performance principles is required.
Be an Early Applicant
The Technical Lead will develop scalable web applications using Angular, mentor junior staff, lead technical teams, and implement best practices. Responsibilities include application design, management of mono repos with NX, and developing robust architectures while ensuring code quality and team collaboration in Agile methodologies.
What you need to know about the Delhi Tech Scene
Delhi, India's capital city, is a place where tradition and progress co-exist. While Old Delhi is known for its rich history and bustling markets, New Delhi is defined by its modern architecture. It's clear the region places a strong emphasis on preserving its cultural heritage while embracing technological advancements, particularly in artificial intelligence, which plays a central role in shaping the city's tech landscape, fueled by investments in research and development.
