Advantest Logo

Advantest

R&D Engineer

Reposted 3 Months Ago
Be an Early Applicant
Remote
Hiring Remotely in IND
Mid level
Remote
Hiring Remotely in IND
Mid level
Design and develop features for the SiConic semiconductor validation platform, implement and optimize test execution, DFT integration, and automation. Develop and debug test flows and integrate components, collaborate cross-functionally, troubleshoot software/hardware interfaces, contribute to architecture and prototypes, and support validation tooling and automation frameworks.
The summary above was generated by AI
Job Summary & Responsibilities

Design and develop new features and enhancements for the SiConic platform aligned with silicon validation workflows.

Implement and optimize test execution, DFT integration, and automation capabilities.

Develop and debug SiConic test flows for semiconductor validation and bring-up scenarios.

Work on integration of various SiConic components (Explorer, Link, Script, etc.) into a scalable solution.

Collaborate with cross-functional teams to translate customer and product requirements into technical solutions.

Debug complex issues across software, hardware interfaces, and validation environments.

Contribute to architecture, design discussions, and prototype development for new features.

Support development of automation frameworks, scripting, and tooling for validation workflows.

Work closely with validation and application teams to ensure high-quality deliverables and usability.

Preferred Qualifications

2-5 years of industry experience with a Bachelor’s degree in Computer Science, Electrical Engineering

Experience in software development, semiconductor domain, or AI/ML-based systems.

Strong programming expertise in Python with good proficiency in C/C++ for system-level development.

Hands-on experience with Linux environments (RHEL/Ubuntu) and software development workflows.

Solid understanding of software design, debugging, and performance optimization techniques.

Knowledge on digital verification, validation or ATE (Automatic Test Equipment) testing techniques

Structured approach to problem analysis and problem solving

Ability to work with minimum supervision

Profound communication skills to work in an international cross-functional team

Similar Jobs

Yesterday
Remote
Electronics City, Bangalore, Karnataka, IND
Senior level
Senior level
Software • Semiconductor • Manufacturing
Performs SoC DFT architecture, test insertion and verification, ATPG pattern generation, coverage improvement, vector simulation, post-silicon debug, and yield improvement. Collaborates with physical design and STA teams on DFT timing closure and may interact with customers. Requires independent execution, cross-geography teamwork, problem-solving, communication, and supervision of team members.
Top Skills: AtpgDft InsertionJtagMbistPerlShellSiemens FastscanSiemens TestkompressSoc DftStatic Timing Analysis (Sta)Vector Simulation
Yesterday
Remote
Electronics City, Bangalore, Karnataka, IND
Senior level
Senior level
Software • Semiconductor • Manufacturing
Performs SoC DFT architecture, test insertion and verification, ATPG pattern generation, coverage improvement, vector simulation, post-silicon debug, and yield improvement. Collaborates with physical design and STA teams on DFT timing closure, supports customer interactions, and may supervise team members across geographies. Requires strong DFT expertise, debugging skills, scripting knowledge, and familiarity with Mentor Graphics DFT tools.
Top Skills: Automatic Test Pattern Generation (Atpg)Design-For-Test (Dft)JtagMemory Built-In Self-Test (Mbist)Mentor Graphics FastscanMentor Graphics TestkompressPerlPhysical DesignShell ScriptingSocStatic Timing Analysis (Sta)
Yesterday
Remote
Electronics City, Bangalore, Karnataka, IND
Senior level
Senior level
Software • Semiconductor • Manufacturing
Work on SoC DFT activities including architecture, test insertion and verification, ATPG pattern generation, coverage improvement, vector simulation, post-silicon debug, yield improvement, and DFT timing closure. Requires collaboration with physical design and STA teams, customers, and geographically distributed teams. The role also involves independent work and supervising team members.
Top Skills: AtpgDesign For Test (Dft)JtagMbistMentor Graphics FastscanMentor Graphics TestkompressPerlPhysical DesignShell ScriptingSocStatic Timing Analysis (Sta)

What you need to know about the Delhi Tech Scene

Delhi, India's capital city, is a place where tradition and progress co-exist. While Old Delhi is known for its rich history and bustling markets, New Delhi is defined by its modern architecture. It's clear the region places a strong emphasis on preserving its cultural heritage while embracing technological advancements, particularly in artificial intelligence, which plays a central role in shaping the city's tech landscape, fueled by investments in research and development.

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account