Microsoft Logo

Microsoft

Principal Silicon Engineer

Posted 2 Days Ago
Be an Early Applicant
Remote
Hiring Remotely in IN
Senior level
Remote
Hiring Remotely in IN
Senior level
Lead full-chip and package integration for DPU ASICs from early planning through tapeout signoff. Drive die/floorplanning, C4/microbump and RDL optimization, power domain management, vendor collaboration, integration milestones, and resolve power/integration issues across teams.
The summary above was generated by AI
Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.

The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives 

We’re seeking a Full-chip Integration experience professionals with solid understanding of C4/package interfaces, chip finishing, and RDL & power delivery. As part of our DPU silicon team, you’ll take on the challenge of driving our fullchip integration execution from early design exploration to signoff.  You’ll work across teams to define, develop, and drive all aspects of power & signal planning, RDL optimization, and packaging interface.  We’re working on some of the most exciting silicon projects in Microsoft, and you will help us drive our vision.


Responsibilities
  • Take ownership and responsibility for our fullchip/package integration
  • Take an active role in early-phase design planning with die size planning, floorplanning, C4/microbump development, and RDL insertion & optimization
  • Develop, enhance, and maintain full-chip integration methodologies; collaborate with vendors and partners to align workflows with industry practices, address tool-related issues, and improve the reliability and efficiency of full-chip finishing and integration processes.
  • Define & drive to integration milestones across project phases; manage interaction and integration with package team & vendors to ensure continuity of entire system design
  • Manage multiple power domains & islands, ensuring correctness and robustness of the design
  • Ensure a convergent integration process and drive package closure through all phases including final signoff for tapeout
  • Work across teams to identify and resolve power delivery issues, integration issues, etc; provide guidance for floorplan adjustments to address power integrity issues and continuity of the package and board design

Qualifications

Required qualifications:

  • Bachelor’s degree in computer engineering, electrical engineering, or related field
  • 7+ years of physical design experience with focus on C4 integration & chip finishing
  • Experience with ASIC design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime) & Physical Verification tools (e.g., Calibre)

Preferred qualifications:

  • 10+ years of hands-on physical design experience with focus on C4/RDL integration, chip finishing, and signoff
  • Deep expertise in power planning, C4/microbump deployment and chip/package interfaces
  • Proficiency in flow automation, scripting (TCL/Perl) & tool debug
  • Ability to develop & maintain package signoff checklists, to track and report fullchip integration progress through all design phases, and successfully execute chip closure on schedule
  • Demonstrated tapeout experience in TSMC 5nm process or below

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.



Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Microsoft Gurugram, Haryana, IND Office

DLF City Phase 3 Rd, DLF Cyber City, Sector 25 A, Sector 24, Gurugram, Haryana, India, 122002

Microsoft New Delhi, Delhi, IND Office

The Executive Centre, Level 3 B/8, DLF Center, Sansad Marg, Connaught Place, New Delhi, India, 110010

Similar Jobs

6 Hours Ago
In-Office or Remote
Senior level
Senior level
Artificial Intelligence • Fintech • Information Technology • Logistics • Payments • Business Intelligence • Generative AI
Lead technical architecture and administration of Zuora Billing and Revenue. Design and build automations, custom objects, API integrations, and complex subscription models. Manage Zuora environments, monitor performance, and run deployments. Own Salesforce CPQ and NetSuite integrations, troubleshoot syncs, and translate Finance and Sales Ops requirements into scalable technical designs.
Top Skills: ApexData QueryJavaJavaScriptNetSuitePythonSalesforceSalesforce CpqSQLSuitescriptTesorioWorkatoZoqlZuora BillingZuora ConnectorsZuora Netsuite ConnectorZuora Rest ApiZuora Revenue (Revpro)Zuora Soap ApiZuora Workflow
7 Hours Ago
Remote
Gujarat, IND
Senior level
Senior level
Artificial Intelligence • Hardware • Information Technology • Machine Learning
Lead packaging assembly process development and NPI to improve yield, reliability, and CPK. Use DOE, SPC, Six Sigma, and RCA/FMEA to optimize processes; introduce new materials and equipment; integrate AI/ML and MES data for predictive control and anomaly detection; drive continuous improvement and cross-functional execution.
Top Skills: Ai/MlAnalytics ToolsDoeFmeaIndustry 4.0JmpMesOcapPythonRcaSix SigmaSmart ManufacturingSpcSQL
7 Hours Ago
Remote
Gujarat, IND
Entry level
Entry level
Artificial Intelligence • Hardware • Information Technology • Machine Learning
Support package qualification and reliability operations by executing reliability and electrical tests, reviewing data and recipe setups, completing certifications, collaborating with planners and engineers, maintaining lab safety and 6S standards, and using AI tools to support lab operations and data tasks.
Top Skills: Ai ToolsElectrical TestingExcelHastHtsMam Tracking SystemMicrosoft OutlookTemperature CyclingThsUhast

What you need to know about the Delhi Tech Scene

Delhi, India's capital city, is a place where tradition and progress co-exist. While Old Delhi is known for its rich history and bustling markets, New Delhi is defined by its modern architecture. It's clear the region places a strong emphasis on preserving its cultural heritage while embracing technological advancements, particularly in artificial intelligence, which plays a central role in shaping the city's tech landscape, fueled by investments in research and development.

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account