Teams at EnCharge AI

Lead clock architecture and physical implementation for advanced SoC designs, including clock tree synthesis, SPICE analysis, timing closure, power optimization, clocking IP integration, and methodology development. Collaborate with architecture, RTL, physical design, STA, verification, and sign-off teams. Use industry-standard EDA tools and scripting languages to automate flows, analyze timing data, and ensure predictable silicon implementation from RTL through GDSII.

Leads end-to-end power, performance, and area optimization for AI semiconductor SoCs. Influences architecture, RTL, memory hierarchies, dataflows, floorplanning, multi-voltage domains, synthesis, placement, clock-tree synthesis, routing, and power-analysis workflows. Partners with architecture, RTL, physical design, EDA vendors, and software teams to develop custom methodologies and deliver energy-efficient silicon under stringent PPA constraints.

Develop and optimize AI models for efficient inference on custom silicon. Build fine-tuning pipelines, implement acceleration techniques (quantization, sparsity, distillation), create benchmarking and profiling tools, and collaborate with hardware, compiler, and quantization teams to translate algorithmic improvements into real hardware gains.