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Advantest

R&D Engineer - Senior Devloper

Reposted One Month Ago
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In-Office or Remote
Hiring Remotely in IND
Senior level
In-Office or Remote
Hiring Remotely in IND
Senior level
As a Senior R&D Engineer, you will support semiconductor customers, providing solutions and training on SiConic technology, conducting installations, and collaborating globally to ensure product functionality and quality.
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Job Summary & Responsibilities

Job Description

Advantest is growing their global support team for its Automated Silicon Validation customers. You will support major semiconductor customers of SiConic solutions. Beyond proven soft-skills this role entails applying well-developed skills around chip bring-up and post silicon validation test development, debug and characterization. You will be part of a global team of SiConic engineers in support centers as well as at customer sites.

Your duties

General:

  • Support the roll-out of the new SiConic solution that is based on V93000 technology to customers in your region and also world-wide customer base
  • As a member of the Support Center team, you will consult customers & account teams across your region on the implementation of the SiConic test solution at various customer teams spanning from Silicon Validation (SV), Design Validation(DV), Design-for-Test (DFT) to Test engineering (TE)
  • Share knowledge, technologies, and experience with colleagues and customers
  • Collaborate with colleagues, partners and customers on worldwide projects
  • Train customer engineers on operation of the SiConic solutions
  • Delivery of customer application trainings and technical workshops on Advantest SiConic

Support tasks:

  • Perform installation, integration, maintenance and update of SiConic SW & HW in your region
  • Troubleshooting, diagnose and repair SiConic solution
  • Provide remote or onsite support of (Beta) Customers
  • Ensure product functionality according to the specifications by assisting customers validating newly designed state-of-the-art semiconductors
  • Customer Collaboration: Work closely with customer engineers to apply best practices and achieve task closure strategies
  • Work with world-wide support team to solve engineering problems for customers
  • Develop and debug SiConic test flows for high-tech semiconductor devices
  • Escalation Management by timely raising substantial tickets, evaluating criticality and managing customer expectations
  • Establishing an effective feedback channel to the various customer issues
     

Feedback:

  • Identify and define emerging engineering test requirements in silicon validation departments following leading edge industry chip bring-ups
  • Collect, evaluate and provide customer requirements for consideration in product improvements and new product developments
  • Observing the product quality and liaising with departments locally & overseas.

Team up with R&D and the product definition team identifying & evaluating any gaps in the existing SiConic solution versus customer specific utilization

Preferred Qualifications

Your profile

Must have:

  • University degree in Electronic Engineering (Bachelor’s or Master’s) or equivalent related knowledge
  • Fluent in English (mandatory)
  • Proactive, self-motivated, and able to work independently
  • >5 years’ relevant experience in semiconductor business
  • Proficient in digital verification, validation or ATE (Automatic Test Equipment) testing techniques
  • Basic knowledge of measurement techniques for electronic components (analog and digital)
  • Experience with C/C++, Java, and scripting languages (Perl/Python)
  • Knowledge in Windows, Microsoft Office, UNIX and Redhat/Ubuntu operating system
  • Willingness to acquire new product knowledge in the field of ATE and chip design
  • Distinguished customer facing skills with a pronounced support attitude and solution-oriented mindset
  • Strong communication and presentation skills
  • Ability and motivation to work in cross-functional project teams in a global environment/good team player
  • Flexible for regional travel (up to 20%)

Preferred / optional:

  • ASIC bringup/debug experience
  • Experience with FPGA or other prototyping platforms
  • Knowledgeable on JTAG procedures preferably with Lauterbach
  • Working knowledge of HSIO interfaces like PCIe and USB

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