About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.
What You Can Expect
- You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process.
- You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools.
- Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues.
- Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.
What We're Looking For
- MTech with 5+ years of block level Physical design experience, Or BTech with 6+ years of experience.
- Good understanding of ASIC physical design block level flow covering all stages like synthesis, floorplanning, PNR , signoff STA, PV etc.. with complex clocking structure.
- Ability to work with block front end engineers and full chip designers to analyse and explore physical implementation options to achieve better routability and timing QOR for complex designs.
- Good understanding of STA, Physical verification at block level.
- Experience in scripting and flow development.
- Very good hands on experience in Cadence Innovus, Synopsys Primtime, Calibre tools.
- Flexibility to work with multiple teams across different sites.
- Candidates that are able to join quickly would be highly preferred .
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
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