The Lead Verification Engineer at Cadence will be responsible for analyzing failures related to code check-ins, performing detailed timing analysis, and developing verification environments. Skills in scripting and familiarity with digital logic systems, as well as emulation technologies, are essential.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
B.Tech/M.Tech (EE) – will good knowledge of Digital Logic Systems / Timing Analysis etc
Ability to correlate failures with code checkins and triage failures quickly
Good Knowledge of Verilog and System verilog is desirable .
Good Analytical and Problem solving Skills .
Capability to write scripts in bash/tcl/perl/python
Familarity with UNIX is a plus , so is knowledge of LSF / SGE/ NC or any other compute farm.
Knowledge of emulation and prototyping technologies is a plus .
We’re doing work that matters. Help us solve what others can’t.
Top Skills
Bash
Perl
Python
System Verilog
Tcl
Verilog
Cadence Design Systems Noida, Uttar Pradesh, IND Office
Plot Nos 57 A, B, C, 11 & 10 Noida Special Economic Zone, PO NSEZ -, Noida, India, 201305
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