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Ceragon Networks

FPGA Senior Engineer

Posted Yesterday
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IN
Senior level
IN
Senior level
As an FPGA Senior Engineer, you'll be responsible for all aspects of FPGA design including coding, synthesizing, timing closure, and verification support. You'll collaborate with various teams in developing next generation backhaul communication systems.
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Description

About Company:

Ceragon Networks (https://www.ceragon.com/about-ceragon/) is a company that develops innovative equipment used in wireless data transmission among other software and service solutions. Our systems are based on microwave technology and serve as a cost-effective alternative to fibre optics.

About the role:

Would you like to be part of a group that takes ideas and brings them to a full product? To influence the entire product flow? If you answered yes to these questions – Your place is with us! Ceragon networks develops a complete product, from idea to field installation, while developing the entire technology internally – ASIC, RF chip and FPGA.

FPGAs are in every product, hence requires continuous development, both new designs and legacy. We are looking for FPGA engineer to Join Ceragon FPGA team in India, developing next generation backhaul communication systems.

In this role you will be required to:

All aspects of FPGA design activity: Coding, Synthesizing, mapping and timing closure, verification support and LAB bring up. Participate in FPGA architecture and design for current and next generation products, collaborate with other teams: SW, DV, QA, System etc



Requirements

  • B.E/B Tech degree in Electronic & Communication or Equivalent

5+ years’ experience as an FPGA designer

5+ years’ experience with networking.

Practical knowledge of RTL design, synthesis, timing closure, simulation and verification test benches.

Hardware bring up and debug experience.

Familiarity with high level programming languages like C/C++, System Verilog, Scripts (TCL, Python) – advantage

Excellent system understanding & strong analytical and problem solver abilities.

Experience with UVM verification flow – advantage.

High motivation to excel in career.


Top Skills

C/C++
System Verilog

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